PLDs are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, lookup tables (LUTs), function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to Input/Output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored off-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Some PLDs, such as the Xilinx Virtex™ FPGA, can be programmed to incorporate blocks with pre-designed functionalities, i.e., “cores”. A core can include a predetermined set of configuration bits that program the FPGA to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, DSP functions, memories, storage elements, and math functions. Some cores include an optimally floor planned layout targeted to a specific family of FPGAs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.
The cores may be designed by a particular vendor for evaluation testing that is to be performed by a user (e.g., a potential customer for the cores) over a limited period of time. Generally, several hours of operation is often adequate for the user to make a fair evaluation of the core's utility. Once the evaluation time period expires, however, the core's functionality may be disabled, which causes the core to cease functioning in its intended manner.
Protection circuitry may be used to enforce the expiration of the evaluation period and to prevent the continued use of the core beyond the intended evaluation period. In particular, a counter may be used in conjunction with a comparator, such that when a terminal count is reached, the output of the comparator asserts a deactivation signal, which renders the core non-functional. For example, given a 42-bit counter running at 156.25 MHz, a terminal count starting from a reset condition is reached in approximately 7.8 hours. Thus, the user is given nearly 8 hours in which to evaluate the core for his or her use.
Alternatively, the counter may be replaced with a linear feedback shift register (LFSR), which provides an equivalent amount of time with which to evaluate the core, but protects the enforcement of the evaluation period in a more secure manner. In particular, since the output of the LFSR is pseudo-random, the terminal count becomes more difficult to detect and consequently, more difficult to defeat.
Common with the counter-based and LFSR-based protection circuits, however, is the “inhibit” signal that is generated by the protection circuits to render the evaluation core unusable. If a particularly malevolent user were to locate this inhibit signal, then knowledge of the terminal count would not be necessary to disable the protection circuit. All that is necessary for the user to continue unauthorized access of the evaluation core is to locate the inhibit signal, disconnect it from the inhibit circuitry, and continuously apply a logic signal that maintains the evaluation core in its operational state. Both protection schemes, therefore, provide a single point of weakness, which is relatively easy to defeat.